--------------------------
Informational requirements
--------------------------

.. req:: label
   :id: REQ_INT3_1732092747
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **General information:**

   The clock initialization function is responsible for configuring the system clock to ensure the microcontroller operates at the desired frequency. 
   This process is crucial for synchronizing the core, peripherals, and external interfaces.

.. req:: label
   :id: REQ_INT3_1732355270
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **High-Speed Internal (HSI) Oscillator**: A built-in clock for low-power applications.

.. req:: label
   :id: REQ_INT3_1732355340
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **High-Speed External (HSE) Oscillator**: An external crystal for precise timing.

.. req:: label
   :id: REQ_INT3_1732355371
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **Phase-Locked Loop (PLL)**: A frequency multiplier to achieve higher system clock speeds.


.. req:: label
   :id: REQ_INT3_1732230545
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **PLL Configuration Parameters**:
    - **PLLM**: Divides the input clock to a lower frequency.
    - **PLLN**: Multiplies the divided clock to achieve the desired frequency.
    - **PLLP**: Divides the multiplied clock to produce the final system clock frequency.

.. req:: label
   :id: REQ_INT3_1732230707
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **Target Configuration**:

   The system clock can be configured using the following formula:

   .. math::

      PLLCLK = \frac{f_{\text{INPUT}}}{\text{PLLM}} \times \text{PLLN} / \text{PLLP}

   Where:

   - **finput**: Input clock frequency
   - **PLLM**: Input clock divider.
   - **PLLN**: Multiplier for the intermediate frequency (IF).This is the frequency generated after dividing the input clock by PLLM and multiplying by PLLN.
   - **PLLP**: Divider to achieve the final output frequency.

.. req:: label
   :id: REQ_INT3_1732355713
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   **Intermediate Frequency (IF):** The intermediate frequency is calculated as:

   .. math::

      f_{\text{IF}} = \frac{f_{\text{INPUT}}}{\text{PLLM}} \times \text{PLLN}

   This intermediate frequency is used internally by the **PLL** before the final output frequency is generated by dividing with **PLLP**.

.. req:: label
   :id: REQ_INT3_1732375834
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   The system architecture consists of three main buses:

    - **AHB** (Advanced High-performance Bus)
    - **APB1** (Advanced Peripheral Bus 1)
    - **APB2** (Advanced Peripheral Bus 2)


.. req:: label
   :id: REQ_INT3_1732356104
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   The **AHB (Advanced High-performance Bus)** must operate within the following frequency range to ensure optimal performance for high-speed data transfers:

    - **AHB Frequency Range:** 60 MHz to 120 MHz (This is the valid range when the system is running at maximum clock speed of 84 MHz, where AHB clock is equal to the system clock divided by a certain divider).

.. req:: label
   :id: REQ_INT3_1732356468
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   The **APB1 (Advanced Peripheral Bus 1)** operates at a lower frequency than AHB:

    - **APB1 Frequency Range:** 30 MHz to 42 MHz (This is typically derived from the AHB clock and then divided by a prescaler).

.. req:: label
   :id: REQ_INT3_1732356614
   :status: Draft
   :date-released:
   :priority: Low
   :submitted-by: Muhibija Kavazovic
   :modified-by:
   :category: Informational
   :safety-asil: 
   :references: 
   :verification-and-validation: 

   The **APB2 (Advanced Peripheral Bus 2)** must operate within the following frequency range for correct functionality of peripherals such as SPI, GPIO, and other high-speed devices:

    - **APB2 Frequency Range:** 30 MHz to 84 MHz (This frequency is determined by the system clock, adjusted by a divider for the APB2 bus).