5.1.1.2.2. Functional Requirements

Requirement: Set USART Mode REQ_INT3_1732999989 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall set the M and CLKEN bits in the USART_CR2 register to select the operating mode for the USART.
Requirement: Configure Baud Rate REQ_INT3_1733000284 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall allow the baud rate to be programmed using the USART_BRR register based on the system clock.
Requirement: Enable/Disable Parity Check REQ_INT3_1733000329 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable or disable parity checking by setting the PCE (Parity Control Enable) and PS (Parity Selection) bits.
Requirement: Configure Word Length and Stop Bits REQ_INT3_1733000553 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall allow selection of 8-bit or 9-bit word length and 1 or 2 stop bits by setting the M1, M0, and STOP bits.
Requirement: Enable Data Transmission REQ_INT3_1733000634 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable or disable data transmission by setting the TE bit.
Requirement: Enable Data Reception REQ_INT3_1733000678 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable or disable data reception by setting the RE bit.
Requirement: Enable Transmission Complete Interrupt REQ_INT3_1733000727 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable the transmission complete interrupt by setting the TCIE bit.
Requirement: Enable Reception Complete Interrupt REQ_INT3_1733000772 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable the reception complete interrupt by setting the RXNEIE bit.
Requirement: Support DMA for Transmission REQ_INT3_1733000813 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall support DMA for data transmission when the DMAT bit in the USART_CR3 register is enabled.
Requirement: Support DMA for Reception REQ_INT3_1733000902 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall support DMA for data reception when the DMAR bit in the USART_CR3 register is enabled.
Requirement: Enable Hardware Flow Control REQ_INT3_1733000966 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable RTS (Request to Send) and CTS (Clear to Send) hardware flow control by setting the RTSE and CTSE bits in the USART_CR3 register.
Requirement: Enable LIN Mode REQ_INT3_1733001087 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall enable LIN mode by setting the LINEN bit in the USART_CR2 register.
Requirement: Configure Clock Polarity and Phase REQ_INT3_1733001146 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The system shall configure the clock polarity and phase for synchronous communication using the CPOL and CPHA bits.
Requirement: Enable Clock Source REQ_INT3_1733095930 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

The clock source must be enabled before enabling the USART module.
Requirement: Data Reception via USART_RDR REQ_INT3_1733095967 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

Data must be received through the USART_RDR (Receive Data Register).
Requirement: Framing Error Detection REQ_INT3_1733095996 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Functional
priority: Low
submitted-by: Adna Njuhovic

Framing error detection must be used when validating the integrity of received data in asynchronous communication.