5.1.3.2.1. Informational Requirements for the Timer Module
Timers in the STM32F411 microcontroller are versatile components used for precise time-related tasks. They help with measuring elapsed time, generating pulses, and controlling time-based processes. |
The STM32 microcontrollers include general-purpose timers, advanced-control timers (for PWM), and dedicated timers. |
General-purpose timers TIM2, TIM3, TIM4, and TIM5 are versatile and support PWM generation, input capture, output compare, and event counting. |
The advanced-control timer TIM1 is designed for complex tasks like motor control and advanced PWM generation with features like complementary outputs and dead-time insertion. |
Complementary outputs refer to two outputs that are opposite in polarity, typically used in applications like motor control or H-bridge circuits, where one output is high while the other is low. |
Dead-time insertion introduces a small delay between switching the complementary outputs to prevent short circuits, ensuring that both outputs are never high simultaneously. |
Smaller dedicated timers TIM9, TIM10, and TIM11 are used for specific purposes, such as single-channel PWM or precise time-based operations. |
In the STM32F411, APB1 timers include TIM2, TIM3, TIM4, and TIM5, operating at a frequency of up to 50 MHz, while APB2 timers include TIM1, TIM9, TIM10, and TIM11, running at a frequency of up to 100 MHz. |
Each timer has dedicated output pins that support alternate functions for tasks like PWM or input capture. |
Timer pins are configured for alternate functions using the AF settings in the GPIO registers. |
Enabling the timer clock for TIM2, TIM3, TIM4, and TIM5 can be done by setting the TIMxEN bit in the RCC_APB1ENR register (‘x’ represents the timer number). |
Enabling the timer clock for TIM1, TIM9, TIM10, and TIM11 can be done by setting the TIMxEN bit in the RCC_APB2ENR register (‘x’ represents the timer number). |
TIM1 has four channels. |
TIM1_CH1 is available on pins PA8 and PE9. |
TIM1_CH2 is available on pins PA9 and PE11. |
TIM1_CH3 is available on pins PA10 and PE13. |
TIM1_CH4 is available on pins PA11 and PE14. |
TIM2 has four channels. |
TIM2_CH1 is available on pins PA0, PA5, and PA15. |
TIM2_CH2 is available on pins PA1 and PB3. |
TIM2_CH3 is available on pins PA2 and PB10. |
TIM2_CH4 is available on pins PA3 and PB11. |
TIM3 has four channels. |
TIM3_CH1 is available on pins PA6, PB4, and PC6. |
TIM3_CH2 is available on pins PA7, PB5, and PC7. |
TIM3_CH3 is available on pins PB0 and PC8. |
TIM3_CH4 is available on pins PB1 and PC9. |
TIM4 has four channels. |
TIM4_CH1 is available on pins PB6 and PD12. |
TIM4_CH2 is available on pins PB7 and PD13. |
TIM4_CH3 is available on pins PB8 and PD14. |
TIM4_CH4 is available on pins PB9 and PD15. |
TIM5 has four channels. |
TIM5_CH1 is available on pin PA0. |
TIM5_CH2 is available on pin PA1. |
TIM5_CH3 is available on pin PA2. |
TIM5_CH4 is available on pin PA3. |
TIM9 has two channels. |
TIM9_CH1 is available on pins PA2 and PE5. |
TIM9_CH2 is available on pins PA3 and PE6. |
TIM10 has one channel. |
TIM10_CH1 is available on pin PB8. |
TIM11 has one channel. |
TIM11_CH1 is available on pin PB9. |
Each timer in the STM32F411 can have up to two Capture/Compare Mode Registers (CCMRs), depending on how many channels the timer supports. |
The TIMx_CCMR1 register is used to configure channels 1 and 2. (‘x’ represents the timer number) |
The TIMx_CCMR2 register is responsible for configuring channels 3 and 4. (‘x’ represents the timer number) |
The CCMR register configures the timer channels, including PWM mode, output compare settings, and capture/compare functionality. |
The TIMx_CCMRy register bits include OCxM (output compare mode) and OCxPE (preload enable).(‘x’ represents the timer number, ‘y’ depends on the channel) |
Pulse Width Modulation (PWM) is a technique for generating variable output signals by modifying the duty cycle. In STM32F411, PWM signals are created using timers, which control the output on specific GPIO pins. |
Duty Cycle is the percentage of time the signal remains high during one cycle. For instance, a 50% duty cycle means the signal is high for half of its period. |
Frequency defines how many times the PWM signal cycles from high to low per second. |
Period defines the length of time for one full cycle of the signal — from the start of one pulse to the start of the next pulse. |
PWM generation can use different modes, such as edge-aligned or center-aligned mode, typically configured using advanced-control timers like TIM1. |
The center-aligned mode is a timer mode used to generate a symmetric PWM signal. In this mode, the timer counts up to a specified value and then counts back down, completing a full cycle within the PWM period. |
The edge-aligned mode is a timer mode used to generate a standard PWM signal. In this mode, the timer counts in a single direction (either up or down) during the PWM period. |
To set the PWM frequency, the prescaler and ARR registers need to be configured. These two parameters together define the period and frequency of the PWM signal. |
The timer frequency depends on the APB bus the timer is on (either 50 MHz or 100 MHz). |
The period of the PWM signal is calculated by dividing the timer frequency by the desired PWM signal frequency. Period = Timer Frequency / Desired Frequency. |
The prescaler reduces the timer frequency to ensure the PWM signal period falls within the valid range of 0 to 65535 for a 16-bit timer. |
ARR is the Auto-Reload Register value that determines the timer period. |
The formula for calculating the prescaler: Prescaler = Timer Frequency / (Desired Frequency * Max ARR). Where Max ARR is 65535. |
The prescaler can be set between 0 and 65535. |
The ARR value is calculated using the formula: ARR = [Timer Frequency / (Desired Frequency * Prescaler) ] − 1. |
The ARR value can be set between 0 and 65535 (for a 16-bit timer). |
Prescaler Register (TIMx_PSC) stores the calculated prescaler value. (‘x’ represents the timer number) |
Auto-Reload Register (TIMx_ARR) stores the calculated ARR value. (‘x’ represents the timer number) |
The CCR (Capture/Compare Register) determines the duty cycle of the PWM signal. |
The CCR (Capture/Compare Register) value is calculated as: CCR = [Duty Cycle * (ARR+1)] / 100. |
The calculated CCR value is written into the corresponding TIMx_CCRy register. ( ‘x’ represents the timer number, ‘y’ is the channel number) |
The TIMx_CR1 register is the main control register for configuring and controlling the timer’s behavior. (‘x’ represents the timer number) |
TIMx_CR1_CEN (Counter Enable) bit controls whether the timer is running or stopped. (‘x’ represents the timer number) |
CCER (Capture/Compare Enable Register) register enables the activation of channels for output functionality. |
The CCER register determines the operating mode of the channel, such as PWM, input capture, or output signal for time measurement. |
TIM_CCER_CCyE bit is used to enable the timer channels for output. (‘y’ represents the channel number) |