5.1.3.2.3. Non-Functional Requirements for the Timer Module
The system must enable the timer clock in less than 1 ms. |
The period calculation must be completed with an error margin of less than 1%. |
The prescaler calculation must be completed with an error margin of less than 1%. |
The ARR value calculation must be completed with an error margin of less than 1%. |
The CCR value must be completed with an error margin of less than 1%. |
All calculations should be completed in less than 10 ms. |
The timer must be initiated in less than 1 ms. |
The system must be able to operate for at least 10 million cycles without failure. |
The timer module should operate with a maximum resource consumption of 5% CPU utilization during PWM operations. |
The timer module should use less than 12.8 KB of RAM for the timer configuration. |
The timer module must support PWM frequencies ranging from 1 Hz to 1,53 MHz. |
The timer module must provide a 16-bit resolution for PWM signal generation, allowing for precise control over the duty cycle with a minimum step size of 0.0015% (1/65536). |