5.1.4.2.3. Informational Requirements
The USART (Universal Synchronous and Asynchronous Receiver-Transmitter) is a peripheral module that facilitates serial communication between devices. |
The USART uses a serial protocol to transmit and receive data bit by bit over a single communication line. |
The following USART registers are used in configuring and operating the USART peripheral: - Status Register (USART_SR) - Data Register (USART_DR) - Baud Rate Register (USART_BRR) - Control Register 2 (USART_CR2) - Control Register 3 (USART_CR3) - Guard Time and Prescaler Register (USART_GTPR) |
The USART supports two primary modes of operation: asynchronous and synchronous. |
In asynchronous mode, the USART transmits data without a shared clock, using start and stop bits for data synchronization. |
In synchronous mode, the USART uses a shared clock between devices for faster and more efficient data transfer. |
USART control registers configure settings such as baud rate, data size, mode of operation, parity, and DMA support. |
The baud rate determines the speed of data transfer in bits per second and is configurable through the Baud Rate Register (BRR).Formula is fPCLK / (8 * (2-OVER8) * USARTDIV) wjere fPCLK is the frequency of clock, OVER8 configuration of oversampling and USARTDIV value om the BRR register. |
The USART provides error detection through parity control, supporting even, odd, and no parity modes. |
The USART integrates Direct Memory Access (DMA) to enhance data transfer efficiency and reduce CPU load. |
The USART can operate in single-wire mode, using one pin for both data transmission and reception. |
The USART supports half-duplex communication, where data transmission and reception occur on the same line but not simultaneously. |
The synchronous mode of USART relies on a shared clock signal to synchronize data transfer between devices. |
The USART transmitter sends data to an external device through the TX (transmit) pin. |
The USART receiver accepts incoming data from an external device through the RX (receive) pin. |
The USART supports oversampling modes (8x and 16x) to improve signal accuracy and communication reliability. |
The USART includes error detection features like frame errors, parity errors, and noise detection for reliable communication. |
The USART peripheral operates with an external clock, which must be enabled before configuration. |
For USART1, the TX and RX pins are mapped to PA9 and PA10, respectively. |
For USART2, the TX and RX pins are mapped to PA2 and PA3, respectively. |
For USART6, the TX and RX pins are mapped to PC6 and PC7, respectively. |
The USART TX and RX pins must be configured as alternate functions for serial communication. |
The USART_BRR register is used to configure the baud rate by setting the mantissa and fraction bits for accurate timing. |
Data is read from or written to the USART_DR register during the transmission or reception of data. |
The CR1 register controls essential USART parameters such as enabling transmission (TE) and reception (RE) and enabling the USART itself (UE). |
The TE bit in CR1 is used to enable the transmitter, and the RE bit is used to enable the receiver for USART operation. |
Data transmission through USART starts with a start bit (low level) followed by data and ends with one or two stop bits (high level). |
The USART frame consists of an idle line, a start bit, data bits (8 or 9 bits), and a configurable stop bit. |
The USART can generate interrupts based on different events such as data register empty, transmission complete, or error conditions. |
Direct Memory Access (DMA) can be used with USART to buffer data for faster data transmission and reception. |
USART supports wakeup from mute mode through address detection or idle line detection. |
In multiprocessor communication mode, the USART detects address frames and supports communication with multiple devices. |
Mute mode allows the USART to ignore incoming data, typically for noise reduction or when the receiver is unavailable. |
The USART may include FIFO buffers for both transmit and receive operations, improving data throughput by reducing interrupt frequency. |
The USART can operate in low power mode, reducing power consumption when idle or during transmission breaks. |
The USART can wake up from stop mode by detecting an active signal on the receiver pin or by address detection. |
The length of a data frame is configurable between 7 and 9 data bits, depending on the system’s requirements. |
The USART receiver has an optional time-out feature to stop reception if no data is received for a configured period. |
The clock polarity and phase can be configured for different data transfer modes (e.g., SPI compatibility mode). |
The USART supports low-noise design with built-in noise suppression to improve data integrity during transmission. |
The USART can operate in different modes, including asynchronous, synchronous, and half-duplex modes. |
The USART supports multiple communication protocols, such as full-duplex, half-duplex, and multi-processor communication. |
Flow control can be enabled in USART to manage data transmission, using either hardware or software control mechanisms. |
The USART is capable of detecting the end of frame conditions, such as the stop bit, for proper synchronization of data communication. |