5.1.5.1.2. Functional requirements
The system shall support the High-Speed Internal (HSI) oscillator as a clock source. |
The system shall support the High-Speed External (HSE) oscillator as a clock source. |
The system shall allow software selection of HSE (25 MHz) as the primary clock source by setting the HSEON bit in the RCC_CR register to 1. |
The system shall confirm HSE stabilization by waiting for the HSERDY bit in the RCC_CR register to be set to 1. |
The system shall configure the PLL to use the HSE as its input source by setting the PLLSRC bit in the RCC_PLLCFGR register to 1. |
The system shall divide the HSE input frequency down to 1 MHz by setting the PLLM field in the RCC_PLLCFGR register to 25 |
The system shall multiply the 1 MHz intermediate frequency up to 200 MHz by setting the PLLN field in the RCC_PLLCFGR register to 200. |
The system shall divide the 200 MHz PLL output frequency by 2 to achieve a 100 MHz system clock by setting the PLLP field in the RCC_PLLCFGR register to 00 |
The system shall enable the PLL by setting the PLLON bit in the RCC_CR register to 1 |
The system shall confirm PLL lock and stabilization by waiting for the PLLRDY bit in the RCC_CR register to be set to 1. |
The system shall set the PLL output as the system clock by configuring the SW field in the RCC_CFGR register. |
The system shall configure the prescalers to ensure that the AHB, APB1, and APB2 buses operate within their maximum allowable frequency limits. |
The system must provide a mechanism to detect clock initialization failures, including PLL and HSE initialization issues, within 2 milliseconds. |
The system shall detect and handle HSE startup failures by falling back to HSI if the HSE fails to stabilize |
The system shall detect and handle PLL lock failures by falling back to HSI if the PLL fails to stabilize. |