5.1.5.2.1. Informational requirements
The Timer module is a key peripheral in STM32F411 microcontrollers, designed to perform operations such as delay generation, event counting, frequency measurement, and Pulse Width Modulation (PWM) signal generation. |
Timer modules depend on the system clock for their operation. Proper configuration of the system clock is crucial to ensure accurate timing, particularly in applications requiring precise control, such as motor speed regulation and signal generation. |
TIM1, TIM9, TIM10, and TIM11 are located on the APB2 bus. |
TIM2, TIM3, TIM4, and TIM5 are located on the APB1 bus. |
Each Timer module supports up to four independent channels for PWM signal generation. |
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TIM2 Pin Mapping (AF1)
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TIM3 Pin Mapping (AF2)
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TIM4 Pin Mapping (AF2)
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TIM5 Pin Mapping (AF2)
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TIM9 Pin Mapping (AF3)
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TIM10 Pin Mapping (AF3)
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TIM11 Pin Mapping (AF3)
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Registers that are key to configuring and operating the Timer Module for generating PWM signals:
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The Prescaler Register (PSC) divides the input clock frequency to achieve a lower timer frequency. The division factor is determined by the value written to the PSC register as PSC+1. For example, if the system clock is 16 MHz and PSC=15, the timer clock becomes 16 MHz/(15+1)= 1 MHz. |
The Auto-Reload Register (ARR) defines the maximum count value the timer can reach before it resets. This value directly determines the period of the PWM signal. For instance, if the timer clock is 1 MHz and ARR=999, the PWM signal period is 1/(999+1)= 1 kHz. |
The Capture/Compare Register specifies the duration the output remains “ON” during one PWM period. This value is calculated based on the input duty cycle and the ARR value:
For example, if a duty cycle is 25% and ARR=999:
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Registers used for PWM configuration include:
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The Capture/Compare Mode Register (CCMR) controls the configuration of TIMER channels. TIM_CCMR1 configures channels 1 and 2, while TIM_CCMR2 configures channels 3 and 4. PWM Mode 1 is activated by setting the OCxM bits to 110. This register defines the mode of operation for each channel, such as PWM mode or input/output signal measurement. |
The Capture/Compare Enable Register (CCER) enables or disables output functionalities for specific TIMER channels. Activation fields include:
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The Control Register (CR1) starts the TIMER counter by setting the CEN bit in the TIM_CR1 register. |
\[f_{PWM} = \frac{f_{TIM}}{(ARR + 1) \times (PSC + 1)}\]
Where:
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Timer channels are independently configurable, allowing simultaneous PWM signal generation with different frequencies and duty cycles. For example, TIM1 supports four channels that can operate independently or in coordination. |
PWM signals have numerous applications, such as motor speed control, where varying duty cycles adjust speed; LED dimming, where duty cycles control brightness; and generating signals for communication protocols like UART or SPI. |
Error handling is important to keep the Timer working correctly. Invalid settings, like duty cycles not between 0% and 100%, should be detected and blocked. If the system clock changes, Timer parameters like PSC, ARR, and CCR must be updated to keep the timing accurate. |