5.1.7.2.1. Informational Requirements

Requirement: label REQ_INT3_1733103223 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

USART is a module that enables serial communication between devices.
Requirement: label REQ_INT3_1733103301 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

There are three USART peripherals and their configuration is as follows:
USART1:

  • TX: PA9 or PB6

  • RX: PA10 or PB7

  • Alternate Function: AF7

USART2:

  • TX: PA2 or PD5

  • RX: PA3 or PD6

  • Alternate Function: AF7

USART6:

  • TX: PC6 or PG14

  • RX: PC7 or PG9

  • Alternate Function: AF8

Requirement: label REQ_INT3_1733103416 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

The two modes of USART are synchronous and asynchronous.
Requirement: label REQ_INT3_1733103482 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Asynchronous mode uses start and stop bits to indicate the beginning and end of transmission.
Requirement: label REQ_INT3_1733103590 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Asynchronous mode does not require a clock line.
Requirement: label REQ_INT3_1733103646 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Synchronous mode uses a clock line between the devices.
Requirement: label REQ_INT3_1733103697 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

In synchronous mode both devices send and receive data.
Requirement: label REQ_INT3_1733103757 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic
Baut rate is the speed of data transmission between two devices.

Baut rate = fplck / (8*(2-OVER8)*USARTDIV)

In this formula, fplck is our clock frequency, OVER8 is the oversampling configuration and USARTDIV is the value in BRR.
Requirement: label REQ_INT3_1733104064 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

BRR: Baud Rate Register, used to set the baud rate for communication.
Requirement: label REQ_INT3_1733104129 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Oversampling is a process where the data is sampled multiple times during one bit of transmission.
Requirement: label REQ_INT3_1733104213 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Oversampling is used in order to get better accuracy in asynchronous mode.
Requirement: label REQ_INT3_1733104268 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

16x oversampling (1) is the standard mode which enables a stable signal.
Requirement: label REQ_INT3_1733104313 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

8x oversampling (0) enables a faster data transmission and is not as precise.
Requirement: label REQ_INT3_1733104379 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Oversampling is adjusted in CR1.
Requirement: label REQ_INT3_1733104430 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

CR1 is used to configure the parameters of USART.
Requirement: label REQ_INT3_1733104500 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

The bits in CR1 are: UE (USART enable), TE (Transmitter enable), RE (Receiver enable).
Requirement: label REQ_INT3_1733104568 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

UE enables or disables USART.
Requirement: label REQ_INT3_1733104625 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

TE enables or disables data transmission.
Requirement: label REQ_INT3_1733104671 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

RE enables or disables data reception.
Requirement: label REQ_INT3_1733104728 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

RXNE bit in USART_SR is used to check if the byte of data is available (1) or not available (0).
Requirement: label REQ_INT3_1733104807 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

RCC: Reset and Clock Control, used to enable the clock for USART.
Requirement: label REQ_INT3_1733104848 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

DR: Data Register, used to hold data to be transmitted.
Requirement: label REQ_INT3_1733104896 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

SR: Status Register, used to check the status of the USART, including the TXE (Transmit Data Register Empty) flag.
Requirement: label REQ_INT3_1733104950 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

TXE (Transfer Data Register Empty) is a bit in the USART_SR.
Requirement: label REQ_INT3_1733105027 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

If TXE is 1 the register is empty and a new byte can be sent.
Requirement: label REQ_INT3_1733105082 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

TC (Transmission Complete) is a bit in USART_SR.
Requirement: label REQ_INT3_1733105145 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

If the value of TC is 1 the byte was successfully sent and the transfer is done.
Requirement: label REQ_INT3_1733105209 ../../../../../_images/arrow-right-circle.svg
status: Draft
style: red_bar
category: Informational
priority: Low
submitted-by: Tarik Sinanovic

Uncorrupted data means that no changes in data occurred in the transmission process.