5.1.2.1.1. Informational Requirements
The RCC (Reset and Clock Control) is responsible for controlling and configuring the clock system of the STM32F411 microcontroller. It manages clock sources, system clock selection, and prescalers for peripheral buses. |
The CR (Control Register) enables or disables various clock sources, such as HSI, HSE, and PLL, and monitors their readiness. |
The PLLCFGR (PLL Configuration Register) allows configuration of the PLL by setting multipliers, dividers, and selecting the input clock source. It determines the final PLL output frequency. |
Possible clock sources for the STM32F411 microcontroller include HSI (High-Speed Internal Oscillator), HSE (High-Speed External Oscillator), and PLL (Phase-Locked Loop). |
The CFGR (Clock Configuration Register) configures the system clock source and sets prescalers for the AHB, APB1, and APB2 buses. |
The HSI (High-Speed Internal Oscillator) provides a fixed internal clock frequency of 16 MHz and serves as the default clock source upon reset. |
The HSE (High-Speed External Oscillator) is an external clock source with a typical range of 4 MHz to 26 MHz, offering high precision and stability. |
The PLL (Phase-Locked Loop) multiplies the frequency of its input clock (HSI or HSE) to generate higher frequencies for the system clock. It is highly configurable through the PLLCFGR register. |
The PLL output frequency is calculated using the formula: f_PLL = (f_input / M) * N / P
- M: PLLM divider (input frequency reduction)
- N: PLLN multiplier (frequency multiplication)
- P: PLLP divider (post-scaling to system clock frequency)
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The AHB (Advanced High-Performance Bus) connects the core processor to high-speed peripherals and system memory. It runs at the system clock frequency (up to 100 MHz in STM32F411). |
The APB1 (Advanced Peripheral Bus 1) bus operates at half the frequency of the AHB bus and supports low-speed peripherals like TIM2, TIM3, and USART2 (up to 50 MHz). |
The APB2 (Advanced Peripheral Bus 2) bus runs at the same frequency as the AHB bus and supports high-speed peripherals like TIM1, TIM8, and USART1 (up to 100 MHz). |
The HSERDY bit in the CR register indicates the readiness of the HSE oscillator. It is set when the oscillator is stable and ready for use. |
The SW field in the CFGR register selects the system clock source, enabling dynamic switching between HSI, HSE, or PLL. |
The SWS field in the CFGR register reflects the currently active system clock source. |
Prescalers (HPRE, PPRE1, and PPRE2) divide the system clock frequency to provide appropriate speeds for the AHB, APB1, and APB2 buses. |
The SystemCoreClockUpdate() function updates the SystemCoreClock variable by reading RCC register settings and recalculating the current system clock frequency. |