5.1.2.1.2. Functional Requirements
The HSEON bit in the RCC_CR register must be set to enable the HSE oscillator. |
The HSERDY bit in the RCC_CR register must be checked to confirm the stability of the HSE oscillator. |
The PLLM field in the RCC_PLLCFGR register must be configured to divide the input clock frequency by 25 to achieve a 1 MHz VCO input frequency. |
The PLLN field in the RCC_PLLCFGR register must be configured to multiply the VCO input frequency by 200 to achieve a 200 MHz VCO output frequency. |
The PLLP field in the RCC_PLLCFGR register must be configured to divide the VCO output frequency by 2 to achieve a 100 MHz system clock. |
The PLLRDY bit in the RCC_CR register must be checked to confirm that the PLL generates a stable clock signal, with an output frequency of 100 MHz. |
The SW field in the RCC_CFGR register must be set to select the PLL as the system clock source. |
The SWS field in the RCC_CFGR register must be checked to confirm that the PLL is the active system clock source. |
The HPRE field in the RCC_CFGR register must be set to 0 (no division). |
The AHB clock frequency must be verified to operate at 100 MHz. |
The PPRE1 field in the RCC_CFGR register must be configured to 4, to divide the clock by 2 for the APB1 prescaler. |
The APB1 clock frequency must be verified to operate at 50 MHz. |
The PPRE2 field in the RCC_CFGR register must be configured to 0 (no division) for the APB2 prescaler. |
The APB2 clock frequency must be confirmed to operate at 100 MHz. |
The HSERDY bit in the RCC_CR register must be set, indicating the HSE oscillator is stable. |
The PLLRDY bit in the RCC_CR register must be set, ensuring that the PLL is stable. |
The SWS field in the RCC_CFGR register must indicate that the PLL is selected as the active system clock source. |
The clock frequencies for the AHB, APB1, and APB2 buses must be verified to operate at 100 MHz, 50 MHz, and 100 MHz, respectively. |
The SystemCoreClock variable must reflect the system clock frequency of 100 MHz, by reading the RCC register settings and calculating the resulting frequency based on the configured SW, HPRE, PPRE1, and PPRE2 fields. |