5.1.2.2.2. Functional Requirements
The TIMxEN bit in the RCC_APB1ENR or RCC_APB2ENR register must be set to enable the timer clock. |
The AFRL or AFRH field in the GPIOx_AFR register must be configured to AF1, AF2, or AF3, based on the timer and channel. |
The PSC register must be written to divide the timer’s input clock frequency to ensure the PWM period fits within the valid range of a 16-bit timer. |
The ARR register must be configured to define the timer period based on the desired PWM frequency and the prescaler value. |
The OCxM bits in the CCMR1 or CCMR2 register must be set to 110 for PWM Mode 1 or 111 for PWM Mode 2 to configure the timer channel’s output behavior. |
The OCxPE (Output Compare Preload Enable) bit in the CCMR1 or CCMR2 register must be set to enable the preload functionality for the CCR register, ensuring synchronized updates with the timer counter and preventing glitches in the PWM signal. |
The CCxE bit in the CCER register must be set to enable the output for the selected timer channel. |
The calculated duty-cycle value must be written to the CCRx register to set the PWM signal’s duty cycle. |
The CEN bit in the TIM_CR1 register must be set to start the timer and begin PWM generation. |