5.1.2.2.1. Informational Requirements
The Reset and Clock Control (RCC) register manages the clock configuration for the STM32F411 microcontroller, including enabling clock signals for timers and peripheral buses. |
The APB1 (Advanced Peripheral Bus 1) supports low-speed peripherals TIM2, TIM3, TIM4, and TIM5 (50 MHz bus). |
The APB2 (Advanced Peripheral Bus 2) supports high-speed peripherals TIM1, TIM9, TIM10, and TIM11 (100 MHz bus). |
The TIMxEN bits in the RCC_APB1ENR and RCC_APB2ENR registers enable the clock for specific timers:
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The GPIOx_MODER register configures the operating mode of GPIO pins. Each pin can be set to:
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The GPIOx_AFR (Alternate Function Register) determines the alternate function of GPIO pins, enabling features such as PWM, input capture, and communication protocols. The register is divided into two sections:
Each pin can be assigned one of 16 alternate functions (AF0 to AF15). |
STM32F411 timers rely on alternate functions to enable features like PWM generation and input capture. The alternate function assignments for timers are:
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The PSC register divides the timer’s input clock frequency to lower the effective timer frequency. Formula: Prescaler = Timer Frequency / (Desired Frequency × ARR_max). Where:
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Pulse Width Modulation (PWM) mode allows the timer to generate a signal with a variable duty cycle. This is achieved by comparing the counter value with the Capture/Compare Register (CCRx). PWM mode can operate in two configurations:
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The OCxM (Output Compare Mode) bits in the CCMR register configure the behavior of the timer output in PWM mode:
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The OCxPE (Output Compare Preload Enable) bit in the CCMR register enables buffering of the CCRx register. This ensures that updates to the CCRx value are synchronized with the timer counter, preventing glitches in the PWM signal. |
The CCxE (Capture/Compare Enable) bit activates the output on the selected timer channel. When this bit is set, the timer output signal is routed to the associated GPIO pin for use in PWM or other timer-based applications. |
The duty cycle is the percentage of time a PWM signal remains high during one period. Formula for Duty Cycle (%): Duty Cycle = (CCRx / (ARR + 1)) × 100. Formula for CCRx: CCRx = (Duty Cycle × (ARR + 1)) / 100. Channel Mapping for CCRx Registers:
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The TIM_CR1 register is responsible for configuring core timer operations, such as counter activation, alignment modes, and update event control. This register ensures proper timer functionality by managing the following operations:
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The CEN (Counter Enable) bit in the TIM_CR1 register controls the start and stop of the timer counter:
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