5.1.3.1.1. Informational Requirements for Clock Initialization Function
RCC Register (Reset and Clock Control) controls clock sources and allows switching between them. It configures the PLL enableling generation of higher frequencies. The RCC Register is charge of reset control for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains. |
AHB (Advanced High-Performance Bus) is a high-speed bus that connects the CPU to peripherals such as memory interfaces, DMA controllers, and interrupt controllers. It operates at the same frequency as the system clock, enabling fast data transfers and supports a single master (the processor) and multiple slaves (peripherals or memory controllers). |
APB (Advanced Peripheral Bus) is a low-speed bus designed for peripherals that do not require high bandwidth, such as UART, I2C, SPI, and GPIO. It operates at a divided frequency of the system clock, which is configurable via prescalers. APB1 and APB2 buses are available, where APB1 is clocked at a lower frequency (up to 50 MHz), and APB2 has a maximum frequency of 100 MHz. |
Prescalers are used to divide the input clock frequency, providing appropriate clock speeds for different parts of the microcontroller, such as buses. |
HSE (High-Speed External) is an external crystal oscillator (up to 25 MHz for STM32F411), providing high precision and stability. It is often used in applications requiring accurate timing. |
RCC_CR Register (Clock Control Register) is central to managing and controlling the activation and readiness of various clock sources in the STM32F411xC. This register contains the HSEON, HSERDY and PLL bit. |
When the RCC_CR_HSEON (High-Speed External Oscillator Enable) bit is set, the hardware begins stabilizing the external clock source. |
The RCC_CR_HSERDY (High-Speed External Oscillator Ready) bit indicates whether the HSE clock source has stabilized and is ready to be used. |
The RCC_CR_PLLON (PLL Enable) bit enables the PLL, which multiplies and divides the input frequency to generate the desired clock frequency. |
PLL (Phase-Locked Loop) enables frequency multiplication to generate higher system clock speeds. It’s key bits are PLLM, PLLN, PLLP. |
PLLM is the division factor for the HSE frequency before multiplication. PLLN is the multiplication factor. PLLP is the division factor after the PLLN result. |
RCC_PLLCFGR Register (PLL Configuration Register) configures the PLL, which generates the main system clock by applying multiplication and division to the input frequency. |
The RCC_PLLCFGR_PLLSRC (PLL Clock Source) bit selects the PLL input source. |
The RCC_PLLCFGR_PLLM (Main PLL Divider) bit sets the division factor for the input clock to generate the PLL input frequency. |
The RCC_PLLCFGR_PLLN (Main PLL Multiplier) bit sets the multiplication factor for the PLL input frequency, generating the VCO frequency. |
The RCC_PLLCFGR_PLLP (Main PLL Output Divider) bit sets the division factor for the VCO output frequency to produce the main system clock. |
RCC_CFGR Register (Clock Configuration Register) selects the system clock source and configures prescalers for the AHB, APB1, and APB2 buses. |
The RCC_CFGR_SW (System Clock Switch) bit selects the system clock source. |
The RCC_CFGR_SWS (System Clock Switch Status) bit indicates the current system clock source. |
The RCC_CFGR_HPRE (AHB Prescaler) bit sets the prescaler for the AHB bus clock. |
The RCC_CFGR_PPRE1 (APB1 Low-Speed Prescaler) bit sets the prescaler for the APB1 bus. The APB1 clock can go up to 50 MHz. |
The RCC_CFGR_PPRE2 (APB2 High-Speed Prescaler) bit sets the prescaler for the APB2 bus. The APB2 clock can go up to 100 MHz. |
The SystemCoreClockUpdate() Function updates the SystemCoreClock variable to reflect the current system clock frequency. |