5.1.3.1.2. Functional Requirements for the Clock Initialization Function

Requirement: label REQ_INT3_1732703613

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must enable the HSE clock source by setting the HSEON bit in the RCC_CR register to 1.

Requirement: label REQ_INT3_1732703739

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must set the PLLN value in the RCC_PLLCFGR register to 200.

Requirement: label REQ_INT3_1732703759

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must set the PLLP value in the RCC_PLLCFGR register to 2.

Requirement: label REQ_INT3_1732703775

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must enable the PLL by setting the PLLON bit in the RCC_CR register to 1.

Requirement: label REQ_INT3_1732703807

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must set the system clock to PLL by setting the SW bits in the RCC_CFGR register to 10.

Requirement: label REQ_INT3_1732703832

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must configure the HPRE bits in the RCC_CFGR register to set the AHB prescaler to 1.

Requirement: label REQ_INT3_1732703880

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must configure the PPRE1 bits in the RCC_CFGR register to set the APB1 prescaler to 2.

Requirement: label REQ_INT3_1732703921

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must configure the PPRE2 bits in the RCC_CFGR register to set the APB2 prescaler to 1.

Requirement: label REQ_INT3_1732704074

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function must implement a timeout mechanism of 1 ms to allow for the stabilization of the HSE and PLL.

Requirement: label REQ_INT3_1732703947

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function shall verify that the HSERDY bit in the RCC_CR register is set to 1.

Requirement: label REQ_INT3_1732704107

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

If the HSERDY bit is not set to 1 within the timeout period of 1 ms, the function must trigger an error-handling mechanism.

Requirement: label REQ_INT3_1732703968

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function shall verify that the PLLRDY bit in the RCC_CR register is set to 1.

Requirement: label REQ_INT3_1732704127

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

If the PLLRDY bit is not set within the timeout period of 1 ms, the function must trigger an error-handling mechanism.

Requirement: label REQ_INT3_1732703982

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function shall verify that the SWS bits in the RCC_CFGR register are set to 10.

Requirement: label REQ_INT3_1732704000

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The function shall call the SystemCoreClockUpdate() function.

Requirement: label REQ_INT3_1732704470

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

The error-handling mechanism must retry the failed operation up to 3 times.

Requirement: label REQ_INT3_1732704139

status: Draft style: red_bar category: Functional priority: Low submitted-by: Emina Mesic

If the error-handling retry attempts fail the 3rd time, the function must return an error code indicating a clock initialization failure.