5.1.3.1.3. Non-Functional Requirements for the Clock Initialization Function
The system must initialize the clock configuration within 2 ms under typical operating conditions. |
The stabilization waiting period for the HSE (HSERDY bit) must not exceed 1 ms. |
The stabilization waiting period for the PLL (PLLRDY bit) must not exceed 1 ms. |
The clock initialization function must support reconfiguration for clock frequencies between 16 MHz to 100 MHz without requiring code changes, provided valid PLLM, PLLN, and PLLP values are supplied. |
The function must accommodate additional clock sources (e.g., MSI, HSI), ensuring modularity. |
The clock frequency deviation after initialization must remain within ±0.01% of the configured 100 MHz value under standard operating conditions. |
Prescalers must be configured to maintain output frequencies of maximum 100 MHz for APB2, to ensure reliable peripheral communication. |
Prescalers must be configured to maintain output frequencies of maximum 50 MHz for APB1, to ensure reliable peripheral communication. |
The on function must use no more than 6 KB of the system’s available RAM for temporary variables. |
The on function must use no more than 1 KB of program memory. |
The function must consume less than 1 ms of the total execution time. |
The function must maintain consistent behavior across at least 100,000 power cycles without degradation. |
The function should be compatible with other STM32 series microcontrollers that share the RCC register structure, requiring the adjustment of register addresses for reuse. |